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32Kx8 LP SRAM EM6132K800W Series GENERAL DESCRIPTION
The EM6132K800W is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The EM6132K800W is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The EM6132K800W operates from a single power supply of 2.7V ~ 5.5V and all inputs and outputs are fully TTL compatible
FEATURES
Fast access time: 35/55/70ns Low power consumption: Operating current: 20/15/10mA (TYP.), VCC = 2.7 ~ 3.6V; 40/35/30mA (TYP.), VCC = 4.5 ~ 5.5V Standby current: -L/-LL version 1/0.5A (TYP.), VCC = 2.7 ~ 3.6V; 2/1A (TYP.), VCC = 4.5 ~ 5.5V Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage: 2.0V (MIN.) Package: 28-pin 600 mil PDIP 28-pin 330 mil SOP 28-pin 8mm x 13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
Vcc Vss A0-A14 DECODER
32Kx8 MEMORY ARRAY
DQ0-DQ7
I/O DATA CURCUIT
COLUMN I/O
CE# WE# OE#
CONTROL CIRCUIT
PIN DESCRIPTION
SYMBOL A0 - A14 DQ0 - DQ7 CE# WE# OE# Vcc Vss DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Power Supply Ground
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32Kx8 LP SRAM EM6132K800W Series PIN CONFIGURATION
PDIP/SOP
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vcc WE# A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
STSOP Type I
OE# A11 A9 A8 A13 WE# Vcc A14 A12 A7 A6 A5 A4 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2
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32Kx8 LP SRAM EM6132K800W Series ABSOLUTE MAXIMUN RATINGS*
PARAMETER Terminal Voltage with Respect to Vss Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM TA TSTG PD IOUT TSOLDER RATING -0.5 to 7.0 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 260 C W mA C C UNIT V
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Output Disable Read Write CE# H L L L OE# X H L X WE# X H H L I/O OPERATION High-Z High-Z DOUT DIN SUPPLY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1
Note: H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
I. Vcc=3.3V PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Average Operating Power supply Current SYMBOL Vcc VIH*1 VIL*2 ILI ILO VOH VOL ICC ICC1 Standby Power Supply Current ISB ISB1 TEST CONDITION MIN. 2.7 2.0 -0.5 -1 -1 2.4 -35 -55 -70 TYP. *5 3.3 3.0 20 15 10 3 1 1 0.5 MAX. 3.6 Vcc+ 0.5 0.6 +1 1 0.4 40 30 20 6 3 40 20*4 UNIT V V V A A V V mA mA mA mA mA A A
Vcc VIN Vss VCC VOUT VSS, Output Disabled IOH = -1mA IOL = 2mA Cycle time = Min. CE# = VIL , II/O = 0mA
Cycle time = 1s CE#0.2V and II/O = 0mA other pins at 0.2V or VCC-0.2V CE# = VIH CE# V VCC - 0.2V -L -LL
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32Kx8 LP SRAM EM6132K800W Series
II. Vcc=5V PARAMETER Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Average Operating Power supply Current
SYMBOL Vcc VIH*1 VIL*2 ILI ILO VOH VOL ICC ICC1
TEST CONDITION
MIN. 4.5 2.0 -0.5 -1 -1 2.4 -35 -55 -70 -
TYP. *5 5.0 40 35 30 5 1 2 1
Vcc VIN Vss VCC VOUT VSS, Output Disabled IOH = -1mA IOL = 2mA Cycle time = Min. CE# = VIL , II/O = 0mA
MAX. 5.5 Vcc+ 0.5 0.8 +1 1 0.4 50 45 40 10 3 100 50*4
UNIT V V V A A V V mA mA mA mA mA A A
Standby Power Supply Current
ISB ISB1
Cycle time = 1s CE#0.2V and II/O = 0mA other pins at 0.2V or VCC-0.2V CE# = VIH CE# V VCC - 0.2V -L -LL
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. 10A for special request 5. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25C
CAPACITANCE (TA = 25C , f = 1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX. 6 8
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA
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32Kx8 LP SRAM EM6132K800W Series AC ELECTRICAL CHARACTERISTICS
READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH MIN. 35 10 5 10 -35 MAX. 35 35 25 15 15 -55 MAX. 55 55 30 20 20 70 MAX. 70 70 35 25 25 UNIT ns ns ns ns ns ns ns ns ns
MIN. 55 10 5 10
MIN. 70 10 5 10
SYM. tWC tAW tCW tAS tWP twr tDW tDH tOW* tWHZ* MIN. 35 30 30 0 25 0 20 0 5 -
-35 MAX. 15
MIN. 55 50 50 0 45 0 25 0 5 -
-55 MAX. 20
MIN. 70 60 60 0 55 0 30 0 5 -
70 MAX. 25
UNIT ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
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32Kx8 LP SRAM EM6132K800W Series TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC Address tAA tOH
Dout
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC Address
tAA CE#
OE#
tACE tOH tOE tOLZ tCLZ tOHZ tCHZ Valid Data
Dout
High-Z
Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
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32Kx8 LP SRAM EM6132K800W Series
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address CE# tAW
tCW WE# tAS tWP tWR
tWHZ Dout (4) tDW High-Z Din WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address CE# tAS tCW WE# tWP tAW Valid Data
tOW (4) tDH
tWR
tWHZ Dout tDW High-Z Din Valid Data tDH High-Z
Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
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32Kx8 LP SRAM EM6132K800W Series DATA RETENTION CHARACTERISTICS
PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL VDR IDR tCDR tR TEST CONDITION CE# V VCC - 0.2V VCC = 1.5V CE# V VCC - 0.2V See Data Retention Waveforms (below) -L -LL MIN. 2.0 0 tRC* TYP. 1 0.5 MAX. 5.5 50 20 UNIT V A A ns ns
DATA RETENTION WAVEFORM
VDR 2.0V
Vcc
Vcc(min.) tCDR CE# Vcc-0.2V
Vcc(min.)
tR
VIH
CE#
VIH
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32Kx8 LP SRAM EM6132K800W Series PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP Package Outline Dimension
28 pin 330 mil SOP Package Outline Dimension
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32Kx8 LP SRAM EM6132K800W Series
28 pin 8mm x 13.4mm STSOP Package Outline Dimension
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32Kx8 LP SRAM EM6132K800W Series
Product Number Information
EM
61
32K
8
0
0
W
S
A
- 35
IF*
Configuration: Option 8: x8 Voltage: 16: x16 V: 3V W: 2.7V Address Density ~5.5V EOREX T: 5V Package: Manufactured S: sTSOP Memory P: PDIP F: SOP
SRAM Family 61: Standard
Version Option Speed: 35ns 55ns 70ns TEMP: Blank: Normal I: Industrial Pb-Free PKG: Blank: Normal F: Pb-free
* Product number example
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32Kx8 LP SRAM EM6132K800W Series
(c)COPYRIGHT 2004 EOREX CORPORATION
The information in this document is subject to change without notice.
Printed in Canada
EOREX makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of EOREX. EOREX subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications.
EOREX CORPORATION http://www.eorex.com sales@eorex.com 2F., No. 301-3, Guang-Ming 6th Rd., Chu-Pei City, Hsinchu County, Taiwan 302, ROC TEL: +886-3-5585138 FAX: +886-3-5585139
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